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litex/migen/bus
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Sebastien Bourdeauducq ebbd5ebcd2 bus/csr/SRAM: better handling of writes to memories larger than the CSR width 2013-05-30 18:45:04 +02:00
..
__init__.py CSR bus definitions 2011-12-05 00:16:44 +01:00
asmibus.py New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
csr.py bus/csr/SRAM: better handling of writes to memories larger than the CSR width 2013-05-30 18:45:04 +02:00
dfi.py New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
memory.py New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
transactions.py New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
wishbone.py Make memory ports part of specials 2013-05-28 16:11:34 +02:00
wishbone2asmi.py Make memory ports part of specials 2013-05-28 16:11:34 +02:00
wishbone2csr.py New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00