Florent Kermarrec d2646f138e csr/CSRStorage: remove alignment_bits: complexify too much code for the few use-cases it's really useful		2019-09-15 19:47:48 +02:00
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__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00
avalon.py	add CONTRIBUTORS file and add copyright header to all files	2019-06-23 23:23:56 +02:00
axi.py	[fix] prevent Vivado from inferring DSP48 in AXIBurst2Beat	2019-08-14 11:30:39 +02:00
csr.py	csr/CSRStorage: remove alignment_bits: complexify too much code for the few use-cases it's really useful	2019-09-15 19:47:48 +02:00
csr_bus.py	soc_core: add csr_alignment to allow 64-bit alignment with 64-bit CPUs	2019-07-08 10:20:51 +02:00
csr_eventmanager.py	add CONTRIBUTORS file and add copyright header to all files	2019-06-23 23:23:56 +02:00
stream.py	soc/interconnect/stream: add Monitor module	2019-09-05 11:54:14 +02:00
stream_packet.py	add CONTRIBUTORS file and add copyright header to all files	2019-06-23 23:23:56 +02:00
stream_sim.py	add CONTRIBUTORS file and add copyright header to all files	2019-06-23 23:23:56 +02:00
wishbone.py	interconnect/wishbone: add FlipFlop to allow UpConverter to be used	2019-09-09 11:47:36 +02:00
wishbone2csr.py	add CONTRIBUTORS file and add copyright header to all files	2019-06-23 23:23:56 +02:00
wishbonebridge.py	add CONTRIBUTORS file and add copyright header to all files	2019-06-23 23:23:56 +02:00