litex/migen
Sebastien Bourdeauducq d2cbc70190 bank/description: memprefix 2013-02-25 23:14:15 +01:00
..
actorlib corelogic -> genlib 2013-02-22 23:19:37 +01:00
bank bank/description: memprefix 2013-02-25 23:14:15 +01:00
bus corelogic -> genlib 2013-02-22 23:19:37 +01:00
fhdl fhdl/specials: allow setting memory name 2013-02-25 23:14:03 +01:00
flow corelogic -> genlib 2013-02-22 23:19:37 +01:00
genlib genlib: clock domain crossing elements 2013-02-23 19:03:35 +01:00
pytholite corelogic -> genlib 2013-02-22 23:19:37 +01:00
sim New 'specials' API 2013-02-22 17:56:35 +01:00
uio uio/ioo: fix specials 2013-02-25 23:13:38 +01:00
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00