Tim 'mithro' Ansell d5a21a7522 Converting litex to use Python modules.		2020-04-11 18:37:06 -07:00
..
boards	targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.	2020-04-10 14:41:01 +02:00
build	litex_sim: Rework Makefiles to put output files in gateware directory.	2020-04-11 18:37:03 -07:00
data	Converting litex to use Python modules.	2020-04-11 18:37:06 -07:00
gen	litex/build: move io.py from litex/gen and re-import DifferentialInput/Output, DDRInput/Output contributed to Migen.	2020-04-10 08:47:07 +02:00
soc	Converting litex to use Python modules.	2020-04-11 18:37:06 -07:00
tools	tools/litex_sim: remove LiteSPI support for now since breaking Travis-CI of others sub-projects.	2020-04-09 11:14:19 +02:00
__init__.py	soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat)	2019-09-30 23:41:07 +02:00