Tim 'mithro' Ansell 5a0bb6ee01 litex_sim: Rework Makefiles to put output files in gateware directory.		2020-04-11 18:37:03 -07:00
..
altera	altera/common: add DDROutput, DDRInput, SDROutput, SDRInput.	2020-04-10 15:50:35 +02:00
lattice	build/lattice/common: remove multi-bits support on SDRInput/Output.	2020-04-10 14:36:13 +02:00
microsemi	build: assume vendor tools are in the PATH and remove automatic sourcing, source and toolchain_path parameters.	2020-03-04 09:13:26 +01:00
sim	litex_sim: Rework Makefiles to put output files in gateware directory.	2020-04-11 18:37:03 -07:00
xilinx	build/xilinx/common: add Spartan6 specialized DDRInput, SDROutput, SDRInput and SDRTristate.	2020-04-10 14:38:22 +02:00
__init__.py
generic_platform.py	litex/build/io: also import CRG (since using DifferentialInput).	2020-04-10 10:25:21 +02:00
generic_programmer.py	add CONTRIBUTORS file and add copyright header to all files	2019-06-23 23:23:56 +02:00
io.py	build/io: add SDR Tristate (with infered version) and remove multi-bits support on SDRIO.	2020-04-10 14:37:29 +02:00
openocd.py	build/openocd: add set_qe parameter to flash	2019-09-12 17:07:56 +02:00
tools.py	build/tools: add replace_in_file function.	2020-03-25 16:36:53 +01:00