litex/litex
Florent Kermarrec d5ad1d56f2 soc/integration: move mem_decoder to soc_core 2020-02-11 17:19:22 +01:00
..
boards platforms/netv2: add pcie pins 2020-01-27 08:25:57 +01:00
build build/sim: allow to use environment's {C,LD}FLAGS 2020-02-04 17:31:31 +01:00
gen gen/fhdl/verilog: fix signed init values 2020-01-12 22:06:35 +01:00
soc soc/integration: move mem_decoder to soc_core 2020-02-11 17:19:22 +01:00
tools tools/litex_sim: use l2_reverse flag 2020-02-03 12:03:57 +01:00
__init__.py soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat) 2019-09-30 23:41:07 +02:00