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d77a5fc5ac
litex
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migen
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bus
History
Florent Kermarrec
71627cf9f0
bus/wishbone: remove size CSR from Cache (L2 size will be reported to the software as a constant)
2015-06-19 08:37:16 +02:00
..
__init__.py
CSR bus definitions
2011-12-05 00:16:44 +01:00
csr.py
global: more pep8
2015-04-13 21:33:44 +02:00
memory.py
global: pep8 (E302)
2015-04-13 20:45:35 +02:00
transactions.py
global: pep8 (E302)
2015-04-13 20:45:35 +02:00
wishbone.py
bus/wishbone: remove size CSR from Cache (L2 size will be reported to the software as a constant)
2015-06-19 08:37:16 +02:00
wishbone2csr.py
global: pep8 (E302)
2015-04-13 20:45:35 +02:00