mirror of
https://github.com/enjoy-digital/litex.git
synced 2025-01-04 09:52:26 -05:00
603b4cdc8c
- rename ft2232h phy to ft245. - make crc optional - fix depacketizer - refactor uart (it's now only a wrapper around standard UART) - fix and update dma
61 lines
1.6 KiB
Python
61 lines
1.6 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.fsm import *
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from migen.actorlib.fifo import *
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from migen.flow.actor import EndpointDescription
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from migen.actorlib.packet import *
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from migen.actorlib.structuring import Pipeline
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packet_header_length = 9
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packet_header_fields = {
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"preamble": HeaderField(0, 0, 32),
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"dst": HeaderField(4, 0, 8),
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"length": HeaderField(5, 0, 32)
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}
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packet_header = Header(packet_header_fields,
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packet_header_length,
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swap_field_bytes=True)
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def phy_description(dw):
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payload_layout = [("data", dw)]
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return EndpointDescription(payload_layout, packetized=False)
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def packet_description(dw):
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param_layout = packet_header.get_layout()
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payload_layout = [
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("data", dw),
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("error", dw//8)
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]
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return EndpointDescription(payload_layout, param_layout, packetized=True)
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def user_description(dw):
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param_layout = [
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("dst", 8),
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("length", 32)
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]
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payload_layout = [
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("data", dw),
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("error", dw//8)
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]
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return EndpointDescription(payload_layout, param_layout, packetized=True)
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class LiteUSBMasterPort:
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def __init__(self, dw):
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self.source = Source(user_description(dw))
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self.sink = Sink(user_description(dw))
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class LiteUSBSlavePort:
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def __init__(self, dw, tag):
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self.sink = Sink(user_description(dw))
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self.source = Source(user_description(dw))
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self.tag = tag
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class LiteUSBUserPort(LiteUSBSlavePort):
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def __init__(self, dw, tag):
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LiteUSBSlavePort.__init__(self, dw, tag)
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