Florent Kermarrec da711ad5f1 liteusb: add simple example design with wishbone bridge and software to control it		2015-05-02 18:21:18 +02:00
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com	liteusb: add simple example design with wishbone bridge and software to control it	2015-05-02 18:21:18 +02:00
cpu	cores: avoid having too much directories when possible (for simple cores or cores contained in a single file)	2015-05-02 16:22:33 +02:00
mem	cores: avoid having too much directories when possible (for simple cores or cores contained in a single file)	2015-05-02 16:22:33 +02:00
others	cores: avoid having too much directories when possible (for simple cores or cores contained in a single file)	2015-05-02 16:22:33 +02:00
soc	rename shadow_address to shadow_base (more appropriate) and use | instead of + (as done in artiq)	2015-05-02 17:07:58 +02:00
tools	litescope/frontend/wishbone: add support for packetized mode	2015-05-02 16:22:43 +02:00
video	global: more pep8	2015-04-13 18:02:26 +02:00
__init__.py	…