litex/litex/soc/interconnect
2019-08-14 11:30:39 +02:00
..
__init__.py
avalon.py add CONTRIBUTORS file and add copyright header to all files 2019-06-23 23:23:56 +02:00
axi.py [fix] prevent Vivado from inferring DSP48 in AXIBurst2Beat 2019-08-14 11:30:39 +02:00
csr.py csr: add assert to ensure CSR size < busword (thanks tweakoz) 2019-07-03 13:44:15 +02:00
csr_bus.py soc_core: add csr_alignment to allow 64-bit alignment with 64-bit CPUs 2019-07-08 10:20:51 +02:00
csr_eventmanager.py add CONTRIBUTORS file and add copyright header to all files 2019-06-23 23:23:56 +02:00
stream.py add CONTRIBUTORS file and add copyright header to all files 2019-06-23 23:23:56 +02:00
stream_packet.py add CONTRIBUTORS file and add copyright header to all files 2019-06-23 23:23:56 +02:00
stream_sim.py add CONTRIBUTORS file and add copyright header to all files 2019-06-23 23:23:56 +02:00
wishbone.py wishbone/SRAM: make read_only emited verilog code compatible with all tools 2019-08-05 09:08:56 +02:00
wishbone2csr.py add CONTRIBUTORS file and add copyright header to all files 2019-06-23 23:23:56 +02:00
wishbonebridge.py add CONTRIBUTORS file and add copyright header to all files 2019-06-23 23:23:56 +02:00