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dd6eacba62
litex
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verilog
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Sebastien Bourdeauducq
c86dd3cbef
Define clock domains instead of passing extra clocks as regular signals
2012-09-11 00:21:07 +02:00
..
generic
framebuffer: fix FIFO read clocking
2012-07-07 11:30:27 +02:00
lm32
LM32: make IP read-only and interrupt lines level-sensitive
2012-02-07 00:07:12 +01:00
m1crg
Define clock domains instead of passing extra clocks as regular signals
2012-09-11 00:21:07 +02:00
minimac3
Remove some boilerplate
2012-05-24 19:22:27 +02:00
s6ddrphy
asmicon: skeleton
2012-03-14 18:26:05 +01:00