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de2f1c31d5
litex
/
targets
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Florent Kermarrec
de2f1c31d5
sdram: create module.py to define SDRAM modules and use it on de0nano/ppro targets
2015-03-21 16:56:53 +01:00
..
__init__.py
add support for external platforms and targets
2013-11-24 16:55:33 +01:00
de0nano.py
sdram: create module.py to define SDRAM modules and use it on de0nano/ppro targets
2015-03-21 16:56:53 +01:00
kc705.py
sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings
2015-03-21 12:55:39 +01:00
mlabs_video.py
sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings
2015-03-21 12:55:39 +01:00
pipistrello.py
sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings
2015-03-21 12:55:39 +01:00
ppro.py
sdram: create module.py to define SDRAM modules and use it on de0nano/ppro targets
2015-03-21 16:56:53 +01:00
simple.py
targets/simple: manual instantiation of CRG (automatic insertion works for BaseSoC but not for MiniSoC since this one define clock_domains)
2015-03-17 01:07:44 +01:00
versa.py
targets: add Lattice ECP3 versa
2015-03-17 19:09:43 +01:00