de2f1c31d5
sdram: create module.py to define SDRAM modules and use it on de0nano/ppro targets
2015-03-21 16:56:53 +01:00
6e4b7c6cfd
sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings
...
req_queue_size, read_time, write_time settings are not sdram_timing settings but sdram controller settings
2015-03-21 12:55:39 +01:00
ec465959d0
pipistrello: add user reset
...
apparently needed for flashed bitstream, xiped bios, mor1kx
2015-03-19 19:01:06 +01:00
a10875a3b7
pipistrello: fix flash, ddram pin naming
2015-03-19 19:01:06 +01:00
9f2e5cd7b6
targets/kc705: add external reset
2015-03-19 15:58:04 +01:00
cb4be52922
targets: add Lattice ECP3 versa
2015-03-17 19:09:43 +01:00
b2f32ad124
targets/simple: manual instantiation of CRG (automatic insertion works for BaseSoC but not for MiniSoC since this one define clock_domains)
2015-03-17 01:07:44 +01:00
28d04ec300
soc: rename with_sdram option to with_main_ram (with_sdram was confusing)
2015-03-14 00:49:19 +01:00
d09529d483
targets/simple: use mibuild default clock
2015-03-14 00:11:59 +01:00
1b72b81f9c
targets/simple: use new generic DifferentialInput
2015-03-12 18:36:04 +01:00
f18ae9b9fe
targets/simple: insert IBUFDS for Xilinx devices (not implemented for others vendors)
2015-03-12 17:25:01 +01:00
e133777450
targets/simple: add MiniSoC
2015-03-06 10:10:58 +01:00
95fa753149
liteeth: add phy autodetect function (phy can still be instanciated directly)
2015-03-06 10:10:34 +01:00
2b9397ff5b
targets: do not implement sdram if already provided by SoC (allow use of -Ot with_sdram = True)
2015-03-06 07:56:45 +01:00
0716dadaf2
targets: keep the SPI flash core even if with_rom is enabled, so that flash booting in the BIOS still works
2015-03-03 10:39:31 +01:00
02ef1dc95a
targets: fix mlabs_video FramebufferSoC
2015-03-02 18:38:43 +01:00
473997df26
cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases)
2015-03-02 16:52:17 +01:00
de698c51e4
sdram: rename self.phy_settings to self.settings (using phy.settings instead of phy.phy_settings seems cleaner)
2015-03-02 11:29:43 +01:00
93b80b2f1c
pipistrello: fix lpddr parameters, crg, flash, style
2015-02-28 16:17:34 -07:00
b32a0e6f9e
liteeth: create example design derived from SoC that can be used on all targets with Ethernet pins
2015-02-28 23:33:00 +01:00
6107b7844a
test implementation on all targets and fix issues
2015-02-28 12:04:51 +01:00
1366ff5e26
move mxcrg to others (we should integrate it in mlabs_video.py and remove the verilog file in the future)
2015-02-28 11:51:51 +01:00
69e869893d
remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)
2015-02-28 11:36:15 +01:00
2c51adcd68
misoclib: better organization (create cores categories: cpu, mem, com, ...)
2015-02-28 09:40:44 +01:00
074f576340
targets: add de0nano (100MHz, integrated bios and SDRAM)
2015-02-27 19:47:32 +01:00
5e2e9338d2
bios: we can now use -Ot with_rom True on targets to force bios implementation in integrated rom (can speed up debug we don't want to reflash SPI or NOR flash)
2015-02-27 17:22:44 +01:00
b031c5edae
targets: fix MiniSoC
2015-02-27 17:12:37 +01:00
07b9cabd0d
gensoc: make it more generic (a SoC does not necessarily have a CPU)
2015-02-27 16:39:00 +01:00
367db268ad
reserve csr_map 0-->16 for gensoc internal csrs
2015-02-27 14:18:13 +01:00
77a6f580e2
gensoc: add check_cpu_memory_region and check_csr_region to detect csr and mem regions conflicts
2015-02-27 10:23:02 +01:00
2b12679ef6
add pipistrello target
2015-02-26 21:35:42 -07:00
a3909bb5e2
Merge branch 'master' of https://github.com/m-labs/misoc
2015-02-26 21:28:12 -07:00
8364fe6674
target/kc705: allow access to pll_sys signal before BUFG
2015-02-26 15:56:10 -07:00
5e8a0c496d
gensoc: add mem_map and mem_decoder to avoid duplications
2015-02-26 20:12:27 +01:00
554731ae44
targets/simple: make it generic (no default_platform, use platform's default_clk_name/default_clk_period)
2015-02-26 13:08:15 +01:00
00862a383c
liteeth: fix import (from liteeth --> from misoclib.liteeth)
2015-02-26 09:48:37 +01:00
73ab271f9a
targets/kc705: fix csr address conflict on eth
2015-02-18 10:45:18 -07:00
0a38b8c74a
add LiteX external core and remove ethmac
2015-02-18 10:43:44 -07:00
9ebb8f8022
remove verilog and move mxcrg.v to misoclib/mxcrg
2015-02-18 10:40:30 -07:00
ceb675c3f1
fix cf92821 merge issue
2014-12-19 21:49:49 +08:00
edb1622668
spiflash: BB write support
2014-11-27 23:10:39 +08:00
cf92821fcf
Refactor directory hierarchy of sdram phys and controllers
2014-11-27 22:09:10 +08:00
33530e0921
ethmac: style/renaming
2014-11-20 18:01:48 -08:00
7eaa5f7372
targets/kc705: avoid ddrphy/ethphy address conflict
2014-11-20 17:11:57 -08:00
603c2641bb
new Ethernet MAC
2014-11-20 16:47:22 -08:00
13fb9282db
targets: add simple design (vendor agnostic and usable on all platforms with UART pins).
...
Designing a SoC with Migen is easy, but we have to provide a very simple design that can
be used on all boards with only 1 clock and 2 UARTs pins defined. This will encourage the
newcomer to invest time in Migen/MiSoC and see its real potential.
2014-09-26 10:35:15 +08:00
c0c17030fd
spi_flash: simplify usage by removing cmd, cmd_width, addr_width parameters
2014-09-04 15:23:39 +08:00
0eeb0ad9eb
targets/kc705: add ddrphy to CSR map
2014-09-01 16:40:10 +08:00
35327a427f
targets/kc705: BIOS XIP
2014-08-22 17:13:10 +08:00
6b35c7b8ea
targets/ppro: reduce SPI flash clock frequency
2014-08-22 15:24:14 +08:00
Florent Kermarrec
Robert Jordens
Sebastien Bourdeauducq
Yann Sionneau