remove verilog and move mxcrg.v to misoclib/mxcrg

2015-02-16 10:22:17 +01:00 · 2015-02-16 10:22:17 +01:00 · 9ebb8f8022
parent 5500c41915
commit 9ebb8f8022
2 changed files with 1 additions and 1 deletions
--- a/misoclib/mxcrg/mxcrg.v
+++ b/misoclib/mxcrg/mxcrg.v
--- a/targets/mlabs_video.py
+++ b/targets/mlabs_video.py
@ -68,7 +68,7 @@ INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";

 PIN "mxcrg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
 """)
-		platform.add_source_dir(os.path.join("verilog", "mxcrg"))
+		platform.add_source_dir(os.path.join("misoclib", "mxcrg"))

 class MiniSoC(BaseSoC):
 	csr_map = {