Tim Callahan e59530ab50 Force SymbiFlow 'make' to be non-parallel. ... Signed-off-by: Tim Callahan <tcal@google.com>		2021-06-15 14:49:28 -07:00
..
build	Force SymbiFlow 'make' to be non-parallel.	2021-06-15 14:49:28 -07:00
compat	compat/stream_sim: Remove TODO since will not be done.	2021-03-24 17:58:13 +01:00
gen	gen/fhdl/verilog: improve clock domain error reporting.	2020-11-10 13:27:29 +01:00
soc	soc/add_video_xy: Allow passing phy or phy's Endpoint.	2021-06-15 18:10:24 +02:00
tools	Sync ROM_BOOT_ADDRESS with main_ram location	2021-06-09 03:36:32 +02:00
__init__.py	revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp).	2020-11-05 19:55:18 +01:00