Florent Kermarrec e03091e7e2 add generic CRCEngine, CRC32, CRCInserter and CRCChecker ... CRCEngine implements a generic and optimized CRC LFSR. It will enable generation of CRC generators and checkers. CRC32 is an implementation of IEEE 802.3 CRC using the CRCEngine. CRC32Inserter and CRC32Checker have been tested on an ethernet MAC.		2014-09-26 11:42:10 +08:00
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actorlib	add generic CRCEngine, CRC32, CRCInserter and CRCChecker	2014-09-26 11:42:10 +08:00
bank	migen/bank/description: add reset parameter to CSRStatus	2014-06-15 23:54:38 +02:00
bus	bus/dfi: add CKE and RESET_N	2014-08-09 10:56:08 +08:00
fhdl	fhdl.structure: do not permit clock domain names that start with numbers	2014-08-18 11:01:56 +08:00
flow	flow/actor: fix eop direction	2014-09-23 00:14:58 +08:00
genlib	add generic CRCEngine, CRC32, CRCInserter and CRCChecker	2014-09-26 11:42:10 +08:00
pytholite	replace use of __dict__ with dir()/xdir()	2013-11-02 16:03:47 +01:00
sim	sim/icarus: add vpi directory to module search path	2014-09-07 16:49:12 +08:00
test	genlib/fifo: add replace command to sync FIFO	2014-09-10 21:19:15 +08:00
util	utils/misc: add gcd_multiple function to compute GCD or any number of integers	2013-12-12 17:36:50 +01:00
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00