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Build your hardware, easily!
3 commits 42 branches 14 tags 31 MiB
C 52.6%
Python 43.7%
Assembly 1.4%
SystemVerilog 1.3%
Makefile 0.3%
Other 0.6%
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Sebastien Bourdeauducq e099f4d52f Reset insertion
2011-12-04 22:41:50 +01:00
migen Reset insertion 2011-12-04 22:41:50 +01:00
.gitignore Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00
test.py Verilog generator 2011-12-04 22:26:32 +01:00