enjoy-digital e0e56e3655 Merge pull request #1 from mithro/master ... Bunch of small fixes		2016-04-19 07:49:24 +02:00
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boards	soc/cores/sdram/settings: simplify modules and fix timing margins computation	2016-04-18 18:22:53 +02:00
build	build/xilinx/ise: use Tim's fix on add_period_constraint and add_false_path_constraint	2016-04-14 21:48:52 +02:00
gen	gen/sim: hack to update vcd output file during simulation (allow visualizing progress directly and having a vcd file even when simulation fails or doesn't stop)	2016-03-25 13:22:26 +01:00
soc	Merge pull request #1 from mithro/master	2016-04-19 07:49:24 +02:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00