Sebastien Bourdeauducq e11d9b9322 bus/wishbone2asmi: cache hits working		2012-02-13 23:11:16 +01:00
..
__init__.py	CSR bus definitions	2011-12-05 00:16:44 +01:00
asmibus.py	Fix syntax errors and other stupid problems	2012-02-13 22:28:02 +01:00
csr.py	bus/csr: Rename a->adr d->dat to be consistent with the other buses	2012-02-13 21:46:39 +01:00
simple.py	Remove explicit bus names and rely on the new automatic namer	2012-01-27 22:20:57 +01:00
wishbone.py	Remove explicit bus names and rely on the new automatic namer	2012-01-27 22:20:57 +01:00
wishbone2asmi.py	bus/wishbone2asmi: cache hits working	2012-02-13 23:11:16 +01:00
wishbone2csr.py	bus/csr: Rename a->adr d->dat to be consistent with the other buses	2012-02-13 21:46:39 +01:00