Sebastien Bourdeauducq e3e1dcd547 dvisampler: add sync polarity detection module (thanks Lars for suggestions)		2013-05-05 11:53:38 +02:00
..
__init__.py	dvisampler: add RawDVISampler	2013-05-04 20:40:21 +02:00
chansync.py	dvisampler/chansync: set synced to 0 when control tokens do not arrive at the same time	2013-04-16 22:21:03 +02:00
charsync.py	Convert to new CSR API	2013-03-30 17:28:15 +01:00
clocking.py	Remove undriven reset signals	2013-04-25 20:19:49 +02:00
common.py	dvisampler: decode before channel sync	2013-03-22 23:49:25 +01:00
datacapture.py	dvisampler/datacapture: swap bit pairs	2013-05-04 20:38:50 +02:00
decoding.py	dvisampler/decoding: hold C when DE=1	2013-05-05 11:51:48 +02:00
edid.py	edid.py: sample SCL only every 64 clock cycles, to avoid bouncing	2013-04-12 22:48:46 +02:00
resdetection.py	Convert to new CSR API	2013-03-30 17:28:15 +01:00
syncpol.py	dvisampler: add sync polarity detection module (thanks Lars for suggestions)	2013-05-05 11:53:38 +02:00