litex/litex
Florent Kermarrec 0f352cd648 soc/cores: use reset_less on datapath/configuration CSRStorages. 2020-04-06 13:17:14 +02:00
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boards targets: netv2: add LiteSPI 2020-04-01 16:20:36 +02:00
build Fix timing constraints 2020-04-05 17:56:29 +02:00
gen gen/fhdl/verilog: fix signed init values 2020-01-12 22:06:35 +01:00
soc soc/cores: use reset_less on datapath/configuration CSRStorages. 2020-04-06 13:17:14 +02:00
tools litex_sim: add LiteSPI 2020-04-01 16:20:36 +02:00
__init__.py soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat) 2019-09-30 23:41:07 +02:00