368 lines
12 KiB
Verilog
368 lines
12 KiB
Verilog
// ==================================================================
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// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
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// ------------------------------------------------------------------
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// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
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// ALL RIGHTS RESERVED
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// ------------------------------------------------------------------
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//
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// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
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//
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// Permission:
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//
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// Lattice Semiconductor grants permission to use this code
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// pursuant to the terms of the Lattice Semiconductor Corporation
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// Open Source License Agreement.
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//
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// Disclaimer:
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//
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// Lattice Semiconductor provides no warranty regarding the use or
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// functionality of this code. It is the user's responsibility to
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// verify the user's design for consistency and functionality through
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// the use of formal verification methods.
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//
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// --------------------------------------------------------------------
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//
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// Lattice Semiconductor Corporation
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// 5555 NE Moore Court
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// Hillsboro, OR 97214
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// U.S.A
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//
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// TEL: 1-800-Lattice (USA and Canada)
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// 503-286-8001 (other locations)
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//
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// web: http://www.latticesemi.com/
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// email: techsupport@latticesemi.com
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//
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// --------------------------------------------------------------------
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// FILE DETAILS
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// Project : LatticeMico32
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// File : lm32_debug.v
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// Title : Hardware debug registers and associated logic.
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// Dependencies : lm32_include.v
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// Version : 6.1.17
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// : Initial Release
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// Version : 7.0SP2, 3.0
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// : No Change
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// Version : 3.1
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// : No Change
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// Version : 3.2
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// : Fixed simulation bug which flares up when number of
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// : watchpoints is zero.
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// =============================================================================
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`include "lm32_include.v"
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`ifdef CFG_DEBUG_ENABLED
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// States for single-step FSM
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`define LM32_DEBUG_SS_STATE_RNG 2:0
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`define LM32_DEBUG_SS_STATE_IDLE 3'b000
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`define LM32_DEBUG_SS_STATE_WAIT_FOR_RET 3'b001
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`define LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN 3'b010
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`define LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT 3'b011
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`define LM32_DEBUG_SS_STATE_RESTART 3'b100
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/////////////////////////////////////////////////////
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// Module interface
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/////////////////////////////////////////////////////
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module lm32_debug (
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// ----- Inputs -------
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clk_i,
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rst_i,
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pc_x,
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load_x,
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store_x,
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load_store_address_x,
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csr_write_enable_x,
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csr_write_data,
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csr_x,
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`ifdef CFG_HW_DEBUG_ENABLED
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jtag_csr_write_enable,
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jtag_csr_write_data,
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jtag_csr,
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`endif
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`ifdef LM32_SINGLE_STEP_ENABLED
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eret_q_x,
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bret_q_x,
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stall_x,
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exception_x,
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q_x,
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`ifdef CFG_DCACHE_ENABLED
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dcache_refill_request,
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`endif
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`endif
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// ----- Outputs -------
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`ifdef LM32_SINGLE_STEP_ENABLED
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dc_ss,
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`endif
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dc_re,
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bp_match,
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wp_match
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);
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/////////////////////////////////////////////////////
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// Parameters
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/////////////////////////////////////////////////////
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parameter breakpoints = 0; // Number of breakpoint CSRs
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parameter watchpoints = 0; // Number of watchpoint CSRs
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/////////////////////////////////////////////////////
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// Inputs
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/////////////////////////////////////////////////////
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input clk_i; // Clock
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input rst_i; // Reset
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input [`LM32_PC_RNG] pc_x; // X stage PC
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input load_x; // Load instruction in X stage
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input store_x; // Store instruction in X stage
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input [`LM32_WORD_RNG] load_store_address_x; // Load or store effective address
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input csr_write_enable_x; // wcsr instruction in X stage
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input [`LM32_WORD_RNG] csr_write_data; // Data to write to CSR
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input [`LM32_CSR_RNG] csr_x; // Which CSR to write
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`ifdef CFG_HW_DEBUG_ENABLED
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input jtag_csr_write_enable; // JTAG interface CSR write enable
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input [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to CSR
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input [`LM32_CSR_RNG] jtag_csr; // Which CSR to write
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`endif
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`ifdef LM32_SINGLE_STEP_ENABLED
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input eret_q_x; // eret instruction in X stage
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input bret_q_x; // bret instruction in X stage
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input stall_x; // Instruction in X stage is stalled
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input exception_x; // An exception has occured in X stage
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input q_x; // Indicates the instruction in the X stage is qualified
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`ifdef CFG_DCACHE_ENABLED
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input dcache_refill_request; // Indicates data cache wants to be refilled
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`endif
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`endif
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/////////////////////////////////////////////////////
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// Outputs
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/////////////////////////////////////////////////////
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`ifdef LM32_SINGLE_STEP_ENABLED
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output dc_ss; // Single-step enable
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reg dc_ss;
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`endif
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output dc_re; // Remap exceptions
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reg dc_re;
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output bp_match; // Indicates a breakpoint has matched
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wire bp_match;
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output wp_match; // Indicates a watchpoint has matched
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wire wp_match;
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/////////////////////////////////////////////////////
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// Internal nets and registers
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/////////////////////////////////////////////////////
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genvar i; // Loop index for generate statements
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// Debug CSRs
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reg [`LM32_PC_RNG] bp_a[0:breakpoints-1]; // Instruction breakpoint address
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reg bp_e[0:breakpoints-1]; // Instruction breakpoint enable
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wire [0:breakpoints-1]bp_match_n; // Indicates if a h/w instruction breakpoint matched
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reg [`LM32_WPC_C_RNG] wpc_c[0:watchpoints-1]; // Watchpoint enable
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reg [`LM32_WORD_RNG] wp[0:watchpoints-1]; // Watchpoint address
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wire [0:watchpoints-1]wp_match_n; // Indicates if a h/w data watchpoint matched
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wire debug_csr_write_enable; // Debug CSR write enable (from either a wcsr instruction of external debugger)
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wire [`LM32_WORD_RNG] debug_csr_write_data; // Data to write to debug CSR
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wire [`LM32_CSR_RNG] debug_csr; // Debug CSR to write to
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`ifdef LM32_SINGLE_STEP_ENABLED
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// FIXME: Declaring this as a reg causes ModelSim 6.1.15b to crash, so use integer for now
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//reg [`LM32_DEBUG_SS_STATE_RNG] state; // State of single-step FSM
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integer state; // State of single-step FSM
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`endif
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/////////////////////////////////////////////////////
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// Functions
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/////////////////////////////////////////////////////
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/////////////////////////////////////////////////////
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// Combinational Logic
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/////////////////////////////////////////////////////
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// Check for breakpoints
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generate
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for (i = 0; i < breakpoints; i = i + 1)
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begin : bp_comb
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assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == `TRUE));
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end
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endgenerate
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generate
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`ifdef LM32_SINGLE_STEP_ENABLED
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if (breakpoints > 0)
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assign bp_match = (|bp_match_n) || (state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT);
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else
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assign bp_match = state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
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`else
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if (breakpoints > 0)
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assign bp_match = |bp_match_n;
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else
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assign bp_match = `FALSE;
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`endif
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endgenerate
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// Check for watchpoints
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generate
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for (i = 0; i < watchpoints; i = i + 1)
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begin : wp_comb
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assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
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end
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endgenerate
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generate
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if (watchpoints > 0)
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assign wp_match = |wp_match_n;
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else
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assign wp_match = `FALSE;
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endgenerate
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`ifdef CFG_HW_DEBUG_ENABLED
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// Multiplex between wcsr instruction writes and debugger writes to the debug CSRs
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assign debug_csr_write_enable = (csr_write_enable_x == `TRUE) || (jtag_csr_write_enable == `TRUE);
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assign debug_csr_write_data = jtag_csr_write_enable == `TRUE ? jtag_csr_write_data : csr_write_data;
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assign debug_csr = jtag_csr_write_enable == `TRUE ? jtag_csr : csr_x;
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`else
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assign debug_csr_write_enable = csr_write_enable_x;
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assign debug_csr_write_data = csr_write_data;
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assign debug_csr = csr_x;
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`endif
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/////////////////////////////////////////////////////
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// Sequential Logic
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/////////////////////////////////////////////////////
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// Breakpoint address and enable CSRs
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generate
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for (i = 0; i < breakpoints; i = i + 1)
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begin : bp_seq
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always @(posedge clk_i `CFG_RESET_SENSITIVITY)
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begin
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if (rst_i == `TRUE)
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begin
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bp_a[i] <= {`LM32_PC_WIDTH{1'bx}};
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bp_e[i] <= `FALSE;
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end
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else
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begin
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if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i))
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begin
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bp_a[i] <= debug_csr_write_data[`LM32_PC_RNG];
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bp_e[i] <= debug_csr_write_data[0];
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end
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end
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end
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end
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endgenerate
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// Watchpoint address and control flags CSRs
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generate
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for (i = 0; i < watchpoints; i = i + 1)
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begin : wp_seq
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always @(posedge clk_i `CFG_RESET_SENSITIVITY)
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begin
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if (rst_i == `TRUE)
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begin
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wp[i] <= {`LM32_WORD_WIDTH{1'bx}};
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wpc_c[i] <= `LM32_WPC_C_DISABLED;
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end
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else
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begin
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if (debug_csr_write_enable == `TRUE)
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begin
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if (debug_csr == `LM32_CSR_DC)
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wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
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if (debug_csr == `LM32_CSR_WP0 + i)
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wp[i] <= debug_csr_write_data;
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end
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end
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end
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end
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endgenerate
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// Remap exceptions control bit
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always @(posedge clk_i `CFG_RESET_SENSITIVITY)
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begin
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if (rst_i == `TRUE)
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dc_re <= `FALSE;
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else
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begin
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if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
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dc_re <= debug_csr_write_data[1];
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end
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end
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`ifdef LM32_SINGLE_STEP_ENABLED
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// Single-step control flag
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always @(posedge clk_i `CFG_RESET_SENSITIVITY)
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begin
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if (rst_i == `TRUE)
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begin
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state <= `LM32_DEBUG_SS_STATE_IDLE;
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dc_ss <= `FALSE;
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end
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else
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begin
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if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
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begin
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dc_ss <= debug_csr_write_data[0];
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if (debug_csr_write_data[0] == `FALSE)
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state <= `LM32_DEBUG_SS_STATE_IDLE;
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else
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state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET;
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end
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case (state)
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`LM32_DEBUG_SS_STATE_WAIT_FOR_RET:
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begin
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// Wait for eret or bret instruction to be executed
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if ( ( (eret_q_x == `TRUE)
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|| (bret_q_x == `TRUE)
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)
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&& (stall_x == `FALSE)
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)
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state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
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end
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`LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN:
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begin
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// Wait for an instruction to be executed
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if ((q_x == `TRUE) && (stall_x == `FALSE))
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state <= `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
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end
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`LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT:
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begin
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// Wait for exception to be raised
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`ifdef CFG_DCACHE_ENABLED
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if (dcache_refill_request == `TRUE)
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state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
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else
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`endif
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if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
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begin
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dc_ss <= `FALSE;
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state <= `LM32_DEBUG_SS_STATE_RESTART;
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end
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end
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`LM32_DEBUG_SS_STATE_RESTART:
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begin
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// Watch to see if stepped instruction is restarted due to a cache miss
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`ifdef CFG_DCACHE_ENABLED
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if (dcache_refill_request == `TRUE)
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state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
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else
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`endif
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state <= `LM32_DEBUG_SS_STATE_IDLE;
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end
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endcase
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end
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end
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`endif
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endmodule
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`endif
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