Florent Kermarrec e48b269d77 build/generic_platform: Fix use_default_clk set when not user provided sys_clk. ... Prevented the default timing constraint to be generated in the timing constraint file.		2021-03-10 10:47:22 +01:00
..
build	build/generic_platform: Fix use_default_clk set when not user provided sys_clk.	2021-03-10 10:47:22 +01:00
gen	gen/fhdl/verilog: improve clock domain error reporting.	2020-11-10 13:27:29 +01:00
soc	soc/cores/gpio: Simplify GPIOIn IRQ, make polarity configurable and also add optional IRQ to GPIOTristate.	2021-03-09 13:57:48 +01:00
tools	tools/litex_sim: Add boot to main_ram when sdram_init contents provided.	2021-02-25 09:10:26 +01:00
__init__.py	revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp).	2020-11-05 19:55:18 +01:00