litex/litex
Florent Kermarrec e61d9eabc6 board/targets/sim: add identifier 2017-06-28 18:08:37 +02:00
..
boards board/targets/sim: add identifier 2017-06-28 18:08:37 +02:00
build litex/build/sim: cleanup modules 2017-06-28 18:01:04 +02:00
gen gen/fhdl/specials: revert migen's commit d98502c6 (specials/Memory: homogenize read-only port syntax) since causing a regression with litepcie 2017-06-10 21:53:53 +02:00
soc soc/cores/identifier: append 0 to contents to indicate end of string 2017-06-22 17:53:19 +02:00
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00