litex/misoclib/mem
Florent Kermarrec e6de4b1bf9 sdram/phy: add simphy (software memtest OK in simulation with MT48LC4M16) 2015-03-26 22:28:32 +01:00
..
flash spiflash: style 2015-03-03 00:54:30 +00:00
litesata litexxx cores: use default baudrate of 115200 for all tests 2015-03-20 12:22:53 +01:00
sdram sdram/phy: add simphy (software memtest OK in simulation with MT48LC4M16) 2015-03-26 22:28:32 +01:00
__init__.py misoclib: better organization (create cores categories: cpu, mem, com, ...) 2015-02-28 09:40:44 +01:00