Sean Cross e7c762c8c3 soc: vexriscv: add cpu debug support ... Add support for debugging the CPU, and gate it behind a new cpu_debug parameter. With this enabled, a simple Wishbone interface is provided. The debug version of the core adds two 32-bit registers to the CPU. The register at address 0 indicates status, and is used to halt and reset the core. The debug register at address 4 is used to inject opcodes into the core, and read back the result. A patched version of OpenOCD can be used to attach to this bus via the Litex Ethernet or UART bridges. Signed-off-by: Sean Cross <sean@xobs.io>		2018-07-05 17:25:28 +08:00
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cores	soc: vexriscv: add cpu debug support	2018-07-05 17:25:28 +08:00
integration	soc_core: remove assert on interrupt (added to catch design issues, but too restrictive for some usecases)	2018-06-19 11:15:29 +02:00
interconnect	replace litex.gen imports with migen imports	2018-02-23 13:38:19 +01:00
software	bios/sdram: also check for last read of scan to choose optimal window	2018-07-02 14:12:27 +02:00
tools	litex_term: cleanup getkey and revert default settings on KeyboardInterrupt	2018-05-24 08:10:05 +02:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00
MISOC_LICENSE	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00