Andrew Dennison e84881072f software/liblitespi: fix building with debug		2023-06-06 10:02:50 +02:00
..
build	build/openfpgaloader: support --fpga-part	2023-06-06 10:02:25 +02:00
compat	compat/soc_core: Fix register_mem/rom missing imports.	2022-11-09 19:11:15 +01:00
gen	gen/fhdl/verilog: Simplify/Rename registers initialization parameter.	2023-05-17 17:24:06 +02:00
soc	software/liblitespi: fix building with debug	2023-06-06 10:02:50 +02:00
tools	litex_client: remove duplicate read	2023-06-06 08:49:54 +02:00
__init__.py	colorer: Avoid duplication and move it to litex/gen.	2022-11-03 09:49:51 +01:00