litex/migen/fhdl
Florent Kermarrec e946f6e453 fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it) 2015-03-16 23:47:07 +01:00
..
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00
bitcontainer.py migen/fhdl/bitcontainer: fix signed arrays (map is an iterator) 2013-12-10 23:32:12 +01:00
decorators.py remove trailing whitespaces 2014-10-17 17:08:46 +08:00
edif.py remove trailing whitespaces 2014-10-17 17:08:46 +08:00
module.py fhdl/visit: fix TransformModule 2015-03-14 17:45:11 +01:00
namer.py remove trailing whitespaces 2014-10-17 17:08:46 +08:00
simplify.py remove trailing whitespaces 2014-10-17 17:08:46 +08:00
specials.py remove trailing whitespaces 2014-10-17 17:08:46 +08:00
std.py fhdl/std: add FinalizeError import 2015-01-23 00:23:41 +08:00
structure.py Raise exception when not using correct boolean operators 2014-10-27 19:40:22 +08:00
tools.py fhdl/tools: do not attempt to rename sync clock domain if it does not exist 2014-11-21 14:51:05 -08:00
tracer.py remove trailing whitespaces 2014-10-17 17:08:46 +08:00
verilog.py fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it) 2015-03-16 23:47:07 +01:00
visit.py fhdl/visit: fix TransformModule 2015-03-14 17:45:11 +01:00