eae0e00496
Hard IP blocks are fixed in location, so long/deep combinational paths routing to multiple hard IP blocks can lead to timing closure problems. XADC and MMCM DRPs currently have their DEN pins triggered by the ".re" output of a CSR. This is asynchronously derived from a fairly complicated set of logic that involves a logic path that goes all the way back through the cache and arbitration mechanisms of the wishbone bus. On more complex designs, this is leading to a failure of timing closure for these paths, because the hard IP blocks can be located in disparate portions of the chip which "pulls" the logic cluster in opposite directions in an attempt to absorb the routing delays to these IP blocks, leading to non-optimal placement for everything else and thus timing closure problems. This pull request proposes that we add a pipeline delay on these critical paths. This delays the commit of the data to the DRP by one cycle, but greatly relieves timing because the pipeline register can be placed close to the cluster of logic that computes addresses, caching, and arbitration, allowing for the routing slack to the hard IP blocks to be absorbed by the path between the pipe register and the hard IP block. In general, this shouldn't be a problem because the algorithm to program the DRP is to hit the write or read CSR, and then poll the drdy bit until it is asserted (so the process is already pretty slow). The MMCM in particular should have almost no impact, because MMCM updates are infrequent and the subsequent lock time of the MMCM is pretty long. The XADC is potentially more problematic because it can produce data at up to 1MSPS; but if sysclk is around 100MHz, adding 10ns to the read latency is relatively small compared to the theoretical maximum data rate of one every 1,000ns. Note that the xadc patch requires introducing a bit of logic into the non-DRP path. This is because without explicitly putting an "if" statement around the logic, you fall back to the non-blocking semantics of the verilog operator, which ultimately leads to a pretty hefty combinational path. By having a default "if" that should get optimized out when DRP is not enabled, when the DRP path /is/ enabled the synthesizer knows it can safely push the async signal into a simple mux as opposed to worrying about enforcing the non-blocking operator semantics to get the desired result. |
||
|---|---|---|
| doc | ||
| litex | ||
| test | ||
| .gitignore | ||
| .gitmodules | ||
| .travis.yml | ||
| CONTRIBUTORS | ||
| LICENSE | ||
| MANIFEST.in | ||
| README.md | ||
| litex_setup.py | ||
| setup.py | ||
README.md
Copyright 2012-2019 / EnjoyDigital
Welcome to LiteX!
LiteX is a FPGA design/SoC builder that can be used to build cores, create SoCs and full FPGA designs.
LiteX is based on Migen and provides specific building/debugging tools for a higher level of abstraction and compatibily with the LiteX core ecosystem.
Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a SoC builder to create/develop/debug FPGA SoCs in Python.
Typical LiteX design flow:
+---------------+
|FPGA toolchains|
+----^-----+----+
| |
+--+-----v--+
+-------+ | |
| Migen +--------> |
+-------+ | | Your design
| LiteX +---> ready to be used!
| |
+----------------------+ | |
|LiteX Cores Ecosystem +--> |
+----------------------+ +-^-------^-+
(Eth, SATA, DRAM, USB, | |
PCIe, Video, etc...) + +
board target
file file
LiteX already supports various softcores CPUs: LM32, Mor1kx, PicoRV32, VexRiscv and is compatible with the LiteX's Cores Ecosystem:
| Name | Build Status | Description |
|---|---|---|
| LiteDRAM |  |
DRAM |
| LiteEth |  |
Ethernet |
| LitePCIe |  |
PCIe |
| LiteSATA |  |
SATA |
| LiteSDCard |  |
SD card |
| LiteICLink |  |
Inter-Chip communication |
| LiteJESD204B |  |
JESD204B |
| LiteVideo |  |
VGA, DVI, HDMI |
| LiteScope |  |
Logic analyzer |
Sub-packages
litex.gen Provides specific or experimental modules to generate HDL that are not integrated in Migen.
litex.build: Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to simulate HDL code or full SoCs.
litex.soc: Provides definitions/modules to build cores (bus, bank, flow), cores and tools to build a SoC from such cores.
litex.boards: Provides platforms and targets for the supported boards. All Migen's platforms can also be used in LiteX. The boards present in the LiteX repository are the official ones that are used for development/CI. More boards are available at: https://github.com/litex-hub/litex-boards
Papers, Presentations, Tutorials, Links
FPGA lessons/tutorials:
OSDA paper/slides:
Linux on LiteX-Vexriscv:
RISC-V Getting Started Guide:
LiteX vs. Vivado First Impressions:
35C3 - Snakes and Rabbits - How CCC shaped an open hardware success:
Tim has to many projects - LatchUp Edition: https://www.youtube.com/watch?v=v7WrTmexod0
Very Quick start guide (for newcomers)
TimVideos.us has done an awesome job for setting up a LiteX environment easily in the litex-buildenv repo: https://github.com/timvideos/litex-buildenv
It's recommended for newcomers to go this way. Various FPGA boards are supported and multiple examples provided! You can even run Linux on your FPGA using LiteX very easily!
Migen documentation can be found here: https://m-labs.hk/migen/manual
Quick start guide (for advanced users)
- Install Python 3.5+ and FPGA vendor's development tools.
- Install Migen/LiteX and the LiteX's cores:
$ wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
$ chmod +x litex_setup.py
$ ./litex_setup.py init install --user (--user to install to user directory)
Later, if you need to update all repositories:
$ ./litex_setup.py update
- Install a RISC-V toolchain:
$ wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
$ tar -xvf riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
$ export PATH=$PATH:$PWD/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14/bin/
-
Build the target of your board...: Go to litex-boards/litex_boards/xxyy/targets (xxyy being community/official/partner) and execute the target you want to build
-
... and/or install Verilator and test LiteX on your computer: Download and install Verilator: http://www.veripool.org/ On Fedora:
$ sudo dnf install libevent-devel json-c-devel
On Ubuntu:
$ sudo apt install libevent-dev libjson-c-dev
$ litex_sim
- Run a terminal program on the board's serial port at 115200 8-N-1. You should get the BIOS prompt.
Contact
E-mail: florent@enjoy-digital.fr