Sebastien Bourdeauducq ee6ca729a2 verilog: user-definable reset and clock		2011-12-16 22:25:05 +01:00
..
bank	fhdl: simpler syntax	2011-12-16 21:30:14 +01:00
bus	fhdl: simpler syntax	2011-12-16 21:30:14 +01:00
corelogic	fhdl: simpler syntax	2011-12-16 21:30:14 +01:00
fhdl	verilog: user-definable reset and clock	2011-12-16 22:25:05 +01:00
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00