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Build your hardware, easily!
52 commits 42 branches 14 tags 31 MiB
C 52.6%
Python 43.7%
Assembly 1.4%
SystemVerilog 1.3%
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Sebastien Bourdeauducq ee6ca729a2 verilog: user-definable reset and clock
2011-12-16 22:25:05 +01:00
examples Pay a bit more attention to PEP8 2011-12-16 16:02:55 +01:00
migen verilog: user-definable reset and clock 2011-12-16 22:25:05 +01:00
.gitignore Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00