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eed8fa374d
litex
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migen
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Sebastien Bourdeauducq
eed8fa374d
fhdl/arrays: use correct BV for intermediate signals
2012-07-11 12:06:32 +02:00
..
actorlib
actorlib/misc/IntSequence: add offset feature
2012-07-07 00:10:23 +02:00
bank
Use super() instead of calling parent constructors directly
2012-06-08 18:06:12 +02:00
bus
bus: CSR initiator
2012-07-07 22:36:15 +02:00
corelogic
fhdl: arrays (TODO: use correct BV for intermediate signals)
2012-07-09 15:16:38 +02:00
fhdl
fhdl/arrays: use correct BV for intermediate signals
2012-07-11 12:06:32 +02:00
flow
flow/perftools: refactor to use hooks
2012-07-06 23:36:23 +02:00
sim
PureSimulable
2012-06-12 17:08:56 +02:00
__init__.py
Initial import, FHDL basic structure, divider example
2011-12-04 16:44:38 +01:00