Florent Kermarrec c27f24c4c0 reorganize code ... - use sys_clk of 166.66MHz and using it instead of sata clk. - rename clocking to CRG since it also handles resets. - create datapath and move code from gtx.		2014-09-27 15:34:28 +02:00
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test.py	reorganize code	2014-09-27 15:34:28 +02:00