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__init__.py
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CSR bus definitions
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2011-12-05 00:16:44 +01:00 |
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asmibus.py
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bus/asmibus/hub: hack to prevent comb loops
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2012-04-30 17:11:42 -05:00 |
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csr.py
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bus: simplify and cleanup
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2012-02-15 16:30:16 +01:00 |
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dfi.py
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bus/dfi: reset active low signals to 1
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2012-04-01 17:43:24 +02:00 |
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simple.py
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bus: add interconnect statements function
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2012-02-17 23:51:32 +01:00 |
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transactions.py
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bus: generic transaction model
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2012-03-08 18:14:06 +01:00 |
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wishbone.py
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bus: generic transaction model
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2012-03-08 18:14:06 +01:00 |
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wishbone2asmi.py
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fhdl: export log2_int
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2012-03-14 12:19:42 +01:00 |
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