litex/litex/soc
enjoy-digital f34593a17d
Merge pull request #421 from betrusted-io/clk0_fractional
add fractional division options to clk0 config on PLL
2020-03-13 14:15:24 +01:00
..
cores Merge pull request #421 from betrusted-io/clk0_fractional 2020-03-13 14:15:24 +01:00
doc Updating the vendored wavedrom js files. 2020-03-12 22:35:04 -07:00
integration soc/intergration: rename mr_memory_x parameter to memory_x. 2020-03-12 12:20:48 +01:00
interconnect Fix copyrights 2020-03-05 17:44:10 +01:00
software software: revert LTO changes (Disable it). 2020-03-11 12:57:00 +01:00
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00