35 lines
1.1 KiB
Python
35 lines
1.1 KiB
Python
from migen.fhdl.structure import *
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class RegisterRaw:
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def __init__(self, name, size=1):
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self.name = name
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self.size = size
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self.re = Signal()
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self.r = Signal(BV(self.size))
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self.w = Signal(BV(self.size))
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(READ_ONLY, WRITE_ONLY, READ_WRITE) = range(3)
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class Field:
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def __init__(self, name, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, reset=0):
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self.name = name
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self.size = size
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self.access_bus = access_bus
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self.access_dev = access_dev
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self.storage = Signal(BV(self.size), reset=reset)
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if self.access_dev == READ_ONLY or self.access_dev == READ_WRITE:
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self.r = Signal(BV(self.size))
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if self.access_dev == WRITE_ONLY or self.access_dev == READ_WRITE:
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self.w = Signal(BV(self.size))
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self.we = Signal()
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class RegisterFields:
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def __init__(self, name, fields):
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self.name = name
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self.fields = fields
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class RegisterField(RegisterFields):
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def __init__(self, name, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, reset=0):
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self.field = Field(name, size, access_bus, access_dev, reset)
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RegisterFields.__init__(self, name, [self.field])
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