Florent Kermarrec f40140dba5 sdram: refactor minicon and fix issues with DDRx memories ... - simplify code - fix AddressSlicer - manage write latency and write to precharge timings - add odt/reset_n signals		2015-05-29 12:31:56 +02:00
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__init__.py	rename shadow_address to shadow_base (more appropriate) and use | instead of + (as done in artiq)	2015-05-02 17:07:58 +02:00
cpuif.py	soc/cpuif: add with_access_functions parameter	2015-04-17 13:26:38 +02:00
sdram.py	sdram: refactor minicon and fix issues with DDRx memories	2015-05-29 12:31:56 +02:00