Florent Kermarrec f43b92103a build/sim/core/Makefile: Add -Wno-COMBDLY and -Wno-CASEINCOMPLETE flags to disable more these warnings (thanks @suarezvictor).		2022-11-07 15:26:35 +01:00
..
build	build/sim/core/Makefile: Add -Wno-COMBDLY and -Wno-CASEINCOMPLETE flags to disable more these warnings (thanks @suarezvictor).	2022-11-07 15:26:35 +01:00
compat	soc_core: Move methods that are no longer recommended to compat_soc_core and add compat_notice to them.	2022-11-03 19:10:31 +01:00
gen	gen/fhdl/verilog: Add Verilog Timescale generation.	2022-11-04 08:15:36 +01:00
soc	build/parser: Add LiteXSoCArgumentParser compatibility and switch to it in integration/soc.	2022-11-07 13:16:24 +01:00
tools	tools/litex_sim: Avoid use of SoCCore.add_memory_region/add_wb_slave.	2022-11-03 19:22:26 +01:00
__init__.py	colorer: Avoid duplication and move it to litex/gen.	2022-11-03 09:49:51 +01:00