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Build your hardware, easily!
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Florent Kermarrec f4cac2c102 Add simulation skeleton 
Remove SRLC16E, will be replaced by distributed ram
 		2012-08-22 23:59:00 +02:00
migScope Add simulation skeleton 2012-08-22 23:59:00 +02:00
sim Add simulation skeleton 2012-08-22 23:59:00 +02:00
spi2Csr new library spi2Csr (skeleton) 2012-08-13 01:02:38 +02:00
README new library spi2Csr (skeleton) 2012-08-13 01:02:38 +02:00
top.py new library spi2Csr (skeleton) 2012-08-13 01:02:38 +02:00

README 

[> migScope
------------

This is a small Logic Analyser to be embedded in a Fpga design to debug internal
or external signals.

[> Status:
Early development phase

[> Contact
E-mail: florent@enjoy-digital.fr