litex/litex
Florent Kermarrec f58e8188b7 soc/cores/i2s: cleanup pass, rename to S7I2SSlave (since 7-Series specific for now), rename fifodepth to fifo_depth for consistency with others cores. 2020-02-06 17:00:04 +01:00
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boards platforms/netv2: add pcie pins 2020-01-27 08:25:57 +01:00
build build/sim: allow to use environment's {C,LD}FLAGS 2020-02-04 17:31:31 +01:00
gen gen/fhdl/verilog: fix signed init values 2020-01-12 22:06:35 +01:00
soc soc/cores/i2s: cleanup pass, rename to S7I2SSlave (since 7-Series specific for now), rename fifodepth to fifo_depth for consistency with others cores. 2020-02-06 17:00:04 +01:00
tools tools/litex_sim: use l2_reverse flag 2020-02-03 12:03:57 +01:00
__init__.py soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat) 2019-09-30 23:41:07 +02:00