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f6e76ae198
litex
/
migen
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bank
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Sebastien Bourdeauducq
d8d4e81b6e
bank/csrgen: fix RE generation
2012-02-18 18:56:18 +01:00
..
__init__.py
Cleanup
2011-12-05 19:25:32 +01:00
csrgen.py
bank/csrgen: fix RE generation
2012-02-18 18:56:18 +01:00
description.py
bank: add RE signal for registers made of fields
2012-02-17 23:52:06 +01:00
eventmanager.py
Use double quotes for all strings
2012-02-14 13:12:43 +01:00