f72f11f7b4
an AsyncFIFO is inserted when clk_domain is not "sys" to enable capture from another clock domain. sys_clk frequency need to be greater than clk_domain clock. future possible improvement: automatic insertion of a converter when clk_domain frequency is greater than sys_clk. |
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.. | ||
host | ||
__init__.py | ||
miio.py | ||
mila.py | ||
std.py | ||
storage.py | ||
trigger.py | ||
uart2wishbone.py |