litex/miscope
Florent Kermarrec f72f11f7b4 mila: add clk_domain support
an AsyncFIFO is inserted when clk_domain is not "sys" to enable capture from another clock domain.
sys_clk frequency need to be greater than clk_domain clock.

future possible improvement: automatic insertion of a converter when clk_domain frequency is
greater than sys_clk.
2014-10-06 12:07:20 +02:00
..
host uart2wishbone: disconnect rx line from shared pads when bridge is selected 2014-08-03 13:15:56 +02:00
__init__.py - reworking WIP 2013-02-22 16:40:49 +01:00
miio.py do some clean up 2014-09-24 22:26:33 +02:00
mila.py mila: add clk_domain support 2014-10-06 12:07:20 +02:00
std.py clean up 2014-08-03 11:44:27 +02:00
storage.py do some clean up 2014-09-24 22:26:33 +02:00
trigger.py do some clean up 2014-09-24 22:26:33 +02:00
uart2wishbone.py use new MiSoC UART with phase accumulators 2014-09-24 21:56:15 +02:00