67 lines
1.8 KiB
Python
67 lines
1.8 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl import verilog
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from migen.bank.description import *
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from miscope.std import *
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from migen.actorlib.fifo import AsyncFIFO
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from miscope.trigger import Trigger
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from miscope.storage import Recorder, RunLengthEncoder
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from mibuild.tools import write_to_file
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class MiLa(Module, AutoCSR):
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def __init__(self, width, depth, ports, with_rle=False, clk_domain="sys"):
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self.width = width
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self.depth = depth
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self.with_rle = with_rle
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self.ports = ports
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self.sink = Record(dat_layout(width))
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if clk_domain is not "sys":
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fifo = AsyncFIFO([("dat", width)], 32) # FIXME: reduce this
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self.submodules += RenameClockDomains(fifo, {"write": clk_domain, "read": "sys"})
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self.comb += [
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fifo.sink.stb.eq(self.sink.stb),
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fifo.sink.dat.eq(self.sink.dat)
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]
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sink = Record(dat_layout(width))
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self.comb += [
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sink.stb.eq(fifo.source.stb),
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sink.dat.eq(fifo.source.dat),
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fifo.source.ack.eq(1)
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]
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else:
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sink = self.sink
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self.submodules.trigger = trigger = Trigger(width, ports)
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self.submodules.recorder = recorder = Recorder(width, depth)
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self.comb += [
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sink.connect(trigger.sink),
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trigger.source.connect(recorder.trig_sink)
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]
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if with_rle:
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self.submodules.rle = rle = RunLengthEncoder(width)
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self.comb += [
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sink.connect(rle.sink),
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rle.source.connect(recorder.dat_sink)
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]
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else:
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sink.connect(recorder.dat_sink)
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def export(self, design, layout, filename):
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ret, ns = verilog.convert(design, return_ns=True)
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r = ""
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def format_line(*args):
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return ",".join(args) + "\n"
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r += format_line("config", "width", str(self.width))
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r += format_line("config", "depth", str(self.depth))
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r += format_line("config", "with_rle", str(int(self.with_rle)))
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for e in layout:
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r += format_line("layout", ns.get_name(e), str(flen(e)))
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write_to_file(filename, r)
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