130 lines
2.6 KiB
Verilog
130 lines
2.6 KiB
Verilog
/*
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* Milkymist SoC
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* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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`timescale 1ns / 1ps
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module tb_norflash();
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reg sys_clk;
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reg sys_rst;
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reg [31:0] wb_adr_i;
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wire [31:0] wb_dat_o;
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reg wb_cyc_i;
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reg wb_stb_i;
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wire wb_ack_o;
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reg [3:0] wb_sel_i;
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wire [23:0] flash_adr;
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wire [15:0] flash_d;
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reg [15:0] flash_do;
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always @(flash_adr) #110 flash_do <= flash_adr[15:0] + 16'b1;
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norflash dut(
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.sys_clk(sys_clk),
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.sys_rst(sys_rst),
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.wishbone_norflash_adr_i(wb_adr_i),
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.wishbone_norflash_dat_o(wb_dat_o),
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.wishbone_norflash_cyc_i(wb_cyc_i),
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.wishbone_norflash_stb_i(wb_stb_i),
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.wishbone_norflash_ack_o(wb_ack_o),
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.wishbone_norflash_sel_i(wb_sel_i),
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.norflash_adr(flash_adr),
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.norflash_d(flash_d),
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.norflash_oe_n(flash_oe_n),
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.norflash_we_n(flash_we_n)
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);
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//assign flash_d = flash_oe_n ? 16'bz : flash_do;
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assign flash_d = flash_do;
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task wbread;
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input [31:0] address;
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integer i;
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begin
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wb_adr_i <= address;
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wb_cyc_i <= 1'b1;
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wb_stb_i <= 1'b1;
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i = 1;
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while(~wb_ack_o) begin
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#5 sys_clk <= 1'b1;
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#5 sys_clk <= 1'b0;
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i = i + 1;
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end
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$display("Read address %h completed in %d cycles, result %h", address, i, wb_dat_o);
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wb_cyc_i <= 1'b0;
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wb_stb_i <= 1'b0;
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/* Let the core release its ack */
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#5 sys_clk <= 1'b1;
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#5 sys_clk <= 1'b0;
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end
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endtask
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initial begin
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$dumpfile("norflash.vcd");
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$dumpvars(1, dut);
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sys_rst <= 1'b1;
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sys_clk <= 1'b0;
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wb_adr_i <= 32'h00000000;
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wb_cyc_i <= 1'b0;
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wb_stb_i <= 1'b0;
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wb_sel_i <= 4'b1111;
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#5 sys_clk <= 1'b1;
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#5 sys_clk <= 1'b0;
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sys_rst <= 1'b0;
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#5 sys_clk <= 1'b1;
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#5 sys_clk <= 1'b0;
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wbread(32'h00000000);
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wbread(32'h00000004);
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wb_sel_i = 4'b0010;
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wbread(32'h0000fff1);
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wb_sel_i = 4'b0100;
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wbread(32'h0000fff2);
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wb_sel_i = 4'b1000;
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wbread(32'h0000fff3);
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wb_sel_i = 4'b0100;
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wbread(32'h0000fff0);
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wb_sel_i = 4'b1111;
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wbread(32'h00000010);
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#5 sys_clk = 1'b1;
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#5 sys_clk = 1'b0;
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#5 sys_clk = 1'b1;
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#5 sys_clk = 1'b0;
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wbread(32'h00000040);
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$finish;
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end
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endmodule
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