Florent Kermarrec f8d6d0fda8 soc/cores/clock/CycloneVPLL: fix typos.		2020-04-08 08:25:46 +02:00
..
boards	targets/de0nano: use CycloneIVPLL, remove 50MHz limitation.	2020-04-07 17:00:45 +02:00
build	Fix timing constraints	2020-04-05 17:56:29 +02:00
gen	gen/fhdl/verilog: fix signed init values	2020-01-12 22:06:35 +01:00
soc	soc/cores/clock/CycloneVPLL: fix typos.	2020-04-08 08:25:46 +02:00
tools	litex_sim: add LiteSPI	2020-04-01 16:20:36 +02:00
__init__.py	soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat)	2019-09-30 23:41:07 +02:00