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In some simulation cases, it's easier to add debug traces directly in the code than in the verilog/Migen testbench. This adds support for verilog $display in Migen code. Being able to terminate a simulation from the code is also useful, this also add support for verilog $finish. |
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| .. | ||
| fhdl | ||
| sim | ||
| __init__.py | ||
| common.py | ||