litex/litex/tools
Michal Sieron 9ae0da667b remote/comm_udp: Fix Etherbone timeout errors
This commit fixes a bug where, retry after timeout would send another
request, but wouldn't discard a response that arrived after the timeout.

Retries worked, but only for dropped packets. If a response arrived, but
`socker.recvfrom` timed out, response would still be put in receive
queue. Later after sending another request, client would try to read
from the socket and would find a response. But this response would be
for the old request.
This way request/response pairs would get misaligned and stop working
properly.

This commit adds read numbering (writes do not have responses).
Numbering is achieved by utilizing the fact that responses to Etherbone
reads are actually writes to an address specified in a request.
This way, we don't need to extend Etherbone protocol, in fact we use it
as it is intended.

This numbering is then used to discard responses that don't match
current request.

I also cleaned setting of the timeout, as it was being set in multiple
places, sometimes to values so small that retry was bound to happen.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
2022-11-14 21:24:37 +01:00
..
remote remote/comm_udp: Fix Etherbone timeout errors 2022-11-14 21:24:37 +01:00
__init__.py tools: move from litex.soc.tools to litex.tools and fix usb.core import 2019-04-20 10:44:53 +02:00
litex_client.py tools/litex_server/litex_client: Add initial information exchange and improve PCIe case. 2022-08-30 18:54:03 +02:00
litex_contributors.py tools/litex_contributors: Sort contributors by names. 2022-09-07 10:07:12 +02:00
litex_json2dts_linux.py cpu/vexriscv_smp/core: Only use Linux variant (Since similar to standard). 2022-05-20 18:52:46 +02:00
litex_json2dts_zephyr.py Add i2s and mmcm handlers 2022-05-26 09:55:14 +02:00
litex_json2renode.py json2renode: cpu: Overhaul generate_cpu 2022-11-08 15:32:09 +01:00
litex_periph_gen.py tools/litex_gen: Rename to litex_periph_gen to make it more explicit (And also to prepare for litex_soc_gen). 2022-05-05 17:36:22 +02:00
litex_read_verilog.py tools/litex_read_verilog: Add proc step before exporting to .json since now seems to be required for some verilog designs. 2022-10-19 15:29:00 +02:00
litex_server.py tools/litex_server/litex_client: Add initial information exchange and improve PCIe case. 2022-08-30 18:54:03 +02:00
litex_sim.py litex_sim: Simplify configuration by creating a temporary config_soc that is then used for the configuration. 2022-11-09 09:24:30 +01:00
litex_soc_gen.py tools/litex_soc_gen: Add identifier, move wb_region to IOs and add optional debug. 2022-05-10 15:16:58 +02:00
litex_term.py tools/litex_server/litex_client: Add initial information exchange and improve PCIe case. 2022-08-30 18:54:03 +02:00