Robert Jordens fe67210d77 migen.fhdl.size: add fiter(), fslice(), and freversed() ... do not overload __len__, __iter__, __reversed__ as not all valid expressions (ints and bools) have them. furthermore len([]) is and should be different from flen([]) (the later raises an error). keep __getitem__ as an exception that proves the rule ;)		2013-12-03 21:36:33 +01:00
..
actorlib	actorlib/spi/DMAWriteController: make ack_when_inactive a keyword-only arg	2013-11-02 23:21:05 +01:00
bank	replace use of __dict__ with dir()/xdir()	2013-11-02 16:03:47 +01:00
bus	bus/wishbone/sram: expose memory component	2013-11-24 23:43:14 +01:00
fhdl	migen.fhdl.size: add fiter(), fslice(), and freversed()	2013-12-03 21:36:33 +01:00
flow	flow/isd: update to new APIs	2013-11-20 17:45:09 +01:00
genlib	genlib/divider: fix diff computation	2013-12-02 17:56:03 +01:00
pytholite	replace use of __dict__ with dir()/xdir()	2013-11-02 16:03:47 +01:00
sim	sim: use Simulator as a contextmanager	2013-11-29 23:05:15 +01:00
test	migen.fhdl.size: add fiter(), fslice(), and freversed()	2013-12-03 21:36:33 +01:00
util	mibuild: use keyword arguments directly in build_cmdline	2013-12-01 17:56:07 +01:00
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00