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https://github.com/enjoy-digital/litex.git
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ffb6081720
litex
/
misoclib
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com
/
liteusb
/
core
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Florent Kermarrec
cb053dc011
liteusb/core/packet: fix missing ,
2015-05-25 13:53:02 +02:00
..
__init__.py
liteusb: continue refactoring (virtual UART and DMA working on minispartan6)
2015-05-01 16:11:15 +02:00
crc.py
liteusb: continue refactoring and add core_tb (should be almost OK)
2015-04-28 18:58:38 +02:00
crossbar.py
liteusb: continue refactoring (virtual UART and DMA working on minispartan6)
2015-05-01 16:11:15 +02:00
packet.py
liteusb/core/packet: fix missing ,
2015-05-25 13:53:02 +02:00