picorv32/scripts/torture/riscv_test.h

#ifndef RISCV_TEST_H
#define RISCV_TEST_H

#define RVTEST_RV32U
#define RVTEST_CODE_BEGIN
#define RVTEST_CODE_END
#define RVTEST_DATA_BEGIN
#define RVTEST_DATA_END

#define RVTEST_FAIL ebreak
#define RVTEST_PASS ebreak

#endif
Added scripts/torture for riscv-torture tests 2016-04-06 10:38:57 -04:00			`#ifndef RISCV_TEST_H`
			`#define RISCV_TEST_H`

			`#define RVTEST_RV32U`
			`#define RVTEST_CODE_BEGIN`
			`#define RVTEST_CODE_END`
			`#define RVTEST_DATA_BEGIN`
			`#define RVTEST_DATA_END`

RISC-V ISA 2.1 now calls "sbreak" officially "ebreak" 2016-06-06 04:46:52 -04:00			`#define RVTEST_FAIL ebreak`
			`#define RVTEST_PASS ebreak`
Added scripts/torture for riscv-torture tests 2016-04-06 10:38:57 -04:00
			`#endif`